The semiconductor manufacturing process comprises many processes. Description will be directed first to a wiring process as an example of a process to which the invention is applied, with reference to FIGS. 1(a) to 1(f).
FIG. 1(a) is a sectional view of a wafer with a first layer of wiring formed thereon. On the surface of a wafer substrate 1 with a transistor portion formed thereon is formed an insulating film 2, on which is further formed a wiring layer 3 such as aluminum for example. For junction with the transistor, contact holes are formed in the insulating film 2 and therefore the portions, indicated at 3', of the wiring layer corresponding to the contact holes are somewhat depressed. In a second-layer wiring process shown in FIG. 1(b), an insulating film 4 and a metal aluminum layer 5 are formed on the first layer, and further, a photoresist film 6 for exposure to make the aluminum layer into a wiring pattern is applied onto the aluminum layer. Next, as shown in FIG. 1(c), a wiring circuit pattern of the second layer is transferred by exposure onto the photoresist film 6 with use of a stepper 7. In this case, if the surface of the photoresist film 6 is concavo-convex, the concave and convex portions, for example the concave portion indicated at 8, on the surface of the photoresist film are not simultaneously in focus, thus resulting in unsatisfactory resolution, which is a serious problem.
For eliminating the above-mentioned inconvenience, the following planarizing process for the substrate surface has been studied. Following the step shown in FIG. 1(a), polishing is applied, after the formation of the insulating layer 4, as shown in FIG. 1(d), by a method as described later so that the layer 4 becomes flat to the level of 9 in the same figure. In this way the state of FIG. 1(e) is obtained. Thereafter, a metal aluminum layer 5 and a photoresist layer 6 are formed, followed by exposure using the stepper 7 as in FIG. 1(f). In this state the foregoing problem of unsatisfactory resolution does not occur.
In FIG. 2 there is illustrated a chemical mechanical polishing method which has heretofore been commonly adopted for planarizing the aforesaid insulating film pattern. A polishing pad 11 is stuck on a surface table 12 and is allowed to rotate. As the polishing pad 11 there is used, for example, a pad obtained by slicing and molding a foamed urethane resin into a thin sheet. A suitable material and fine surface structure are selected from among various materials and fine surface structures according to the type of workpiece and the degree of surface roughness to be attained finally. The wafer 1 to be processed is fixed to a wafer holder 14 through an elastic pressing pad 13. While the wafer holder 14 is rotated, it is pressed against the surface of the polishing pad 11, and a polishing slurry 15 is fed onto the polishing pad, whereby the convex portions of the insulating film 4 on the wafer surface are polished off, thus affording a flat surface.
In the case of polishing such an insulating film as a silicon dioxide film, there usually is employed colloidal silica as the polishing slurry. Colloidal silica is in the form of a suspension of fine silica particles 30 nm or so in diameter in an aqueous alkali solution such as a potassium hydroxide solution. Because of an additional chemical action in the presence of alkali, the use of such colloidal silica is characterized in that an extremely high processing efficiency and a smooth surface with reduced processing damage are obtained in comparison with a mechanical polishing an abrasive alone. This method thus involving the supply of polishing slurry between the polishing pad and the workpiece during processing is well known as a free abrasive polishing technique.
The conventional wafer planarizing technique using such a free abrasive polishing method involves two problems that are difficult to solve when classified broadly. One problem is a pattern size dependence problem such that in a certain type of pattern or a certain state of difference in height, it is impossible to attain planarization to a satisfactory extent. The other problem is an excessively high cost of consumption articles required in the polishing process. These problems will be described below in more detail.
Generally, on a semiconductor wafer are formed patterns having various sizes and differences in height. For example, in the case of a semiconductor memory device, as shown in FIG. 3(a), one chip is divided broadly into four blocks called memory mat portion 16, and in the interior of each block are formed fine memory cells regularly and densely. Along the boundaries of four memory mat portions is formed a peripheral circuit 17 for making access to the above memory cells. In the case of a typical dynamic memory, one chip size is about 7 mm.times.20 mm, and the width of the peripheral circuit 17 is 1 mm or so. In the section of the chip taken on line A-A', as shown in FIG. 3(b), an average height of a memory mat portion 16H is about 0.5 to 1 .mu.m higher than that of a peripheral circuit portion 17L. If an insulating film 4 of about 1 to 2 .mu.m thick is formed on such a stepped pattern, a sectional shape 31 of the surface portion substantially reflects the stepped shape of the base pattern.
In the planarization process contemplated in the present invention, the insulating film 4 on the wafer surface is to be rendered flat, as indicated by a dot-dashline 32. However, in the case of using a soft polishing pad formed of a polyurethane foam often used for the purpose being considered, the planarization intended as above is not attained because the polishing speed involves pattern dependence. More specifically, as shown in FIG. 4, if a soft polishing pad 11L is used, the surface of the polishing pad is deformed, as indicated by a solid line 30 in the figure, due to the polishing load. A fine pattern with a size of the order of micron is polished flat in a short time because of concentration of load, but in the case of a large pattern with a size of the order of millimeter, the polishing speed is low because the load applied thereto is in the form of a distributed load. As a result, the sectional shape after polishing becomes like that indicated by a broken line 34 in the figure, there still remaining a difference in height,d.
Flatness can be improved by making the polishing pad harder, but in this case there arises a new problem of increased unevenness in processing within the wafer plane as well as a problem of processing damage as described later. As to the cause of such an increase of processing unevenness which occurs in the use of a hard pad, it has not been made clear yet scientifically. But it is presumed that the probability of abrasive fed onto the polishing pad surface being captured by fine structural portions on the pad surface and entering between the pad and the substrate to be processed varies, and that this variation exerts an influence on the processing. For the semiconductor wiring process it is required that such unevenness be .+-.5% or less. At present, an upper limit of the polishing pad hardness is about 10 kg/mm.sup.2 in terms of Young's modulus. Therefore, in a semiconductor device wherein a variety of patterns, including small and large patterns, of the order of millimeter to the order of micron are mixed together, like a memory device, it is impossible to expect a satisfactory effect of planarization. For this reason, the products to which such a polishing pad can be applied are limited to semiconductor products not containing a very large pattern, for example a logic LSI.
As a polishing pad having a characteristic intermediate between hard and soft polishing pads, a polishing pad comprising a soft pad and hard polishing pellets embedded in part of the soft pad is disclosed in Japanese Patent Laid Open No. Hei 6-208980. However, the polishing characteristic obtained is almost the same as that of a polishing pad having an intermediate hardness.
The second subject to be attained by the planarization technique for a semiconductor wafer based on the above conventional free abrasive polishing method is the reduction of running cost which is high. This is attributable to a low utilization efficiency of polishing slurry used in the free abrasive polishing method. More particularly, for ultra-smooth polishing not causing polishing flaws, it is necessary that a polishing slurry, for example colloidal silica, be fed at a rate of several hundred cc/min or more. However, the greater part of the slurry is wasted without contributing to the actual processing. The cost of a high purity slurry for semiconductor manufacture is extremely high, and the cost of the planarizing polishing process is mostly dependent on the polishing slurry. Thus, it has been keenly desired to make an improvement on this point.
As a prior art method other than those referred to above, a bonded abrasive processing method, using a grindstone for high-speed rotation is fabricated by binding an abrasive with a metallic powder or a resin, is described on pages 80 to 85 of Proceedings in the 1st International ABTEC Conference (Seoul, November 1993). However, this method is known to involve the drawback that there often occur fine scratches on the processed surface. Further, for solving this problem of scratching, a planarization technique using a fine abrasive grindstone with an extremely small grain diameter fabricated by electrophoresis is disclosed in Japanese Patent Laid Open No. hei 6-302568. According to this technique, however, since the grindstone itself is hard, there still remains the problem of scratching caused by dust or the like contained in the polishing fluid used or in the processing atmosphere.
In the conventional semiconductor wafer planarizing technique using the free abrasive polishing method, as explained above, there exists no condition that permits simultaneous planarization for both a fine pattern of the order of micron in minimum size and a large pattern of the order of millimeter. Thus, it has so far been difficult to apply this conventional technique to the manufacture of a semiconductor integrated circuit including a variety of large and small patterns, like memory LSI. Further, a high running cost required for the polishing process has been a great drawback in its application to mass production.
It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art and provide a processing method for planarizing both large and fine pattern portions into a single plane without causing any processing damage, as well as an apparatus for the processing method.
It is another object of the present invention to provide a processing method that is low in running cost and an apparatus for the processing method.